1. Field of the Invention
The present invention relates to a timing analysis apparatus, a timing analysis method and a program product for a semiconductor integrated circuit, which is particularly preferable for use in static timing analysis in a semiconductor integrated circuit.
2. Description of the Related Art
As a method of conducting timing verification of a semiconductor integrated circuit such as an LSI, especially a digital circuit, static timing analysis (STA) is conventionally used. In the static timing analysis, timing verification of a circuit is conducted based on delays assigned respectively to elements and the like in the circuit, unlike circuit simulation and logical simulation which are conducted to correspond to an actual operation logically.
Namely, in the static timing analysis, creation of a test pattern or the like is not needed, and timing verification is conducted by accumulating a delay of each element and the like in a path (signal flow path). The static timing analysis requires short time for verification, and is capable of comprehensively analyzing an entire chip at one time, and therefore static timing analysis apparatuses are used as one of the verification apparatuses for designs of most of the semiconductor integrated circuits recently.
Here, there are normally variations in the characteristics of the elements in the semiconductor integrated circuit, and it is necessary to carry out static timing analysis in consideration of the variations. At present, static timing analysis is generally carried out by expressing the variation of each element by multiplying the delay of each element by an equal coefficient (for example, refer to Patent document 1 (Japanese Patent Laid-open No. 63-98042), and Patent document 2 (Japanese Patent Laid-open No. 2002-222232). The variation in the delay of each element is expressed in this manner, and it is verified whether the semiconductor integrated circuit is normally operable or not when the variation in the chip occurs.
For example, in the conventional static timing analysis, timing verification of a semiconductor integrated circuit under the worst condition is conducted by verifying whether the conditions expressed by the following expressions (19) and (20) are satisfied or not. Here, the worst condition is the condition under which the circuit operates at a low speed, and corresponds to the case in which process (P) is at a low speed, temperature (T) is high, and voltage (V) is low.Cycle_Time+Clock_path_time×ocv_worst−Data_time−Setup_time>0  (19)Data_path_time×ocv_worst−Clock_path_time−Hold_time>0  (20)
Similarly, timing verification of a semiconductor integrated circuit under the best condition is conducted by verifying whether the conditions shown by the following expressions (21) and (22) are satisfied, or not. The best condition is the condition under which the circuit operates at a high speed, and corresponds to the case in which process (P) is at a high speed, temperature (T) is low, and voltage (V) is high.Cycle_Time+Clock_path_time−Data_path_time×ocv_best−Setup_time>0  (21)Data_path_time−Clock_path_time×ocv_best−Hold_time>0  (22)
The above-described expressions (19) and (21) are conditional expressions for verifying setup time, and the above-described expressions (20) and (22) are conditional expressions for verifying hold time.
In the above-described expressions (19) to (22), Cycle_Time is a cycle of a clock signal, Clock_path_time is a clock path delay, Data_path_time is a data path delay, Setup_time is a value of standard of setup time, Hold_time is a value of standard of hold time, ocv_worst is a variation coefficient under the worst condition, and ocv_best is a variation coefficient under the best condition. The coefficients ocv_worst and ocv_best are constant values which are previously specified to express variations in delay.